\section{Approach}
\label{sec:approach}

\begin{wrapfigure}{r}{0.75\textwidth}
\begin{center}
\vspace{-15mm}
% Requires \usepackage{graphicx}
\includegraphics[width=0.75\textwidth]{./lib/figures/ApproachFigure.pdf}
\end{center}
\vspace{-10mm}
\caption{\small Both within and across each of the two thrusts of our investigation, circuit and architecture-level concerns interact strongly to define the space of optimal designs.}\label{fig:approach}
%\vspace{-3mm}
\end{wrapfigure}

Broadly considered, our project objectives span two distinct
areas. Firstly, using physics-based models, we plan to investigate the architectural implications
of tunnel FET based designs, such as the degree to which device-level variability limits
processor-level operating frequencies, voltage settings, guard bands,
and overall energy savings. These limitations ultimately express
themselves as shifts in which regions of the design space of potential
processor-application pairs are best served by a processor built from
TFETs or from a more traditional technology. Second, we aim to explore
the space of TFET-specific circuit techniques that can either
capitalize on or mitigate the unique properties of TFETs, desired or
unwanted, respectively. Key features of this area include translating
retention-flop techniques to the TFET space, layout optimizations for
TFET-based standard cell designs, and a revisiting of the circuits and
circuit assumptions underlying existing architectural approaches to
tolerate process variation, such as Razor~\cite{Razor}, when moving
from MOSFETs to TFETs. Figure~\ref{fig:approach} shows how these two avenues of investigation interact with each other. Below, we describe both areas in greater
detail.



\input{circuit_architecture_implications}

\input{circuit_architecture_co-design}

% LocalWords:  FET TFETs TFET optimizations MOSFETs
